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Part No.GD25LE80CTJG
MfrGIGADEVICE
Size1Mb
Pages68 pages
Description1.8V Uniform Sector Dual and Quad Serial Flash
Datasheet SummaryAI
1. Chip Overview (GD25LE80C)

️· Type: 1.8V Uniform Sector Flash Memory
️· Key Features: Supports Dual/Quad IO. Includes various protections (block, hardware, OTP, power-down) and a Status Register with configurable behavior.

2. Status Register Bits


Bit(s) Name Function Default Value Notes
S15 SUS1 Erase Suspend indicator (set by Program/Erase Suspend command) 0 Cleared by Program/Erase Resume or power cycle.
S14 CMP Configuration Mode bit - affects Block Protect behavior (see Tables 1 & 1A) 0 Controls how Block Protection is applied.
S13-S11 LB3-LB1 OTP Security Register Control. Set to 1 to lock Security Registers. 0 One-Time Programmable.
S10 SUS2 Program Suspend indicator (set by Program/Erase Suspend command) 0 Cleared by Program/Erase Resume or power cycle.
S9 QE Quad Enable. Controls Quad IO pins (IO2, IO3) and WP#/HOLD# functionality. 0 Set to 0 to enable WP#/HOLD#. Recommended to avoid shorting issues with external circuitry.
S8 SRP1 Status Register Protection bit - Controls how Status Register can be written. 0 Controls Power-Down, Hardware, One-Time Programming lock-down.
S7 SRP0 Status Register Protection bit - controls how Status Register can be written. 0 See SRP1 for details.
S6 BP4 Block Protect bit - Non-volatile. Defines protected memory area. 0 Part of Block Protect scheme.
S5-S3 BP3-BP1 Block Protect bits - Non-volatile. Defines protected memory area. 0 Part of Block Protect scheme.
S2 BP0 Block Protect bit - Non-volatile. Defines protected memory area. 0 Part of Block Protect scheme.
S1 WEL Write Enable Latch - Indicates if the device can accept write commands. 1 Must be 1 to write to status register, program or erase.
S0 WIP Write in Progress - Indicates if the device is busy with a write operation. 0 Must be 0 to initiate a write operation.

3. Protection Features (Important!)

️· Block Protection (BP0-BP4): Define a protected area within the flash. Requires Write Status Register command.
️· Hardware Protection (SRP1, SRP0): Controlled by an external pin (#WP).
️· Power-Down Lock-Down (SRP1, SRP0): Prevents modification of the Status Register until a power cycle.
️· One-Time Programmable Protection (SRP1, SRP0): Prevents any future modification of the Status Register.
️· Security Registers (LB3-LB1): Locked using the LB bits. Once locked, they become read-only.

4. Key Commands/Operations and their Impact

️· Write Status Register (WRSR): Used to modify Status Register bits (except WIP and WEL).
️· Program/Erase Suspend (75H): Sets the SUS1 bit.
️· Program/Erase Resume (7AH): Clears SUS1 and SUS2 bits.
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    • Datasheet Details
    Part No.GD25LE80CTJG
    ManufacturerGIGADEVICE
    Size1Mb
    Pages68 pages
    Description1.8V Uniform Sector Dual and Quad Serial Flash
    Datasheet Summary AI Expand summary
    1. Chip Overview (GD25LE80C)

    ️· Type: 1.8V Uniform Sector Flash Memory
    ️· Key Features: Supports Dual/Quad IO. Includes various protections (block, hardware, OTP, power-down) and a Status Register with configurable behavior.

    2. Status Register Bits


    Bit(s) Name Function Default Value Notes
    S15 SUS1 Erase Suspend indicator (set by Program/Erase Suspend command) 0 Cleared by Program/Erase Resume or power cycle.
    S14 CMP Configuration Mode bit - affects Block Protect behavior (see Tables 1 & 1A) 0 Controls how Block Protection is applied.
    S13-S11 LB3-LB1 OTP Security Register Control. Set to 1 to lock Security Registers. 0 One-Time Programmable.
    S10 SUS2 Program Suspend indicator (set by Program/Erase Suspend command) 0 Cleared by Program/Erase Resume or power cycle.
    S9 QE Quad Enable. Controls Quad IO pins (IO2, IO3) and WP#/HOLD# functionality. 0 Set to 0 to enable WP#/HOLD#. Recommended to avoid shorting issues with external circuitry.
    S8 SRP1 Status Register Protection bit - Controls how Status Register can be written. 0 Controls Power-Down, Hardware, One-Time Programming lock-down.
    S7 SRP0 Status Register Protection bit - controls how Status Register can be written. 0 See SRP1 for details.
    S6 BP4 Block Protect bit - Non-volatile. Defines protected memory area. 0 Part of Block Protect scheme.
    S5-S3 BP3-BP1 Block Protect bits - Non-volatile. Defines protected memory area. 0 Part of Block Protect scheme.
    S2 BP0 Block Protect bit - Non-volatile. Defines protected memory area. 0 Part of Block Protect scheme.
    S1 WEL Write Enable Latch - Indicates if the device can accept write commands. 1 Must be 1 to write to status register, program or erase.
    S0 WIP Write in Progress - Indicates if the device is busy with a write operation. 0 Must be 0 to initiate a write operation.

    3. Protection Features (Important!)

    ️· Block Protection (BP0-BP4): Define a protected area within the flash. Requires Write Status Register command.
    ️· Hardware Protection (SRP1, SRP0): Controlled by an external pin (#WP).
    ️· Power-Down Lock-Down (SRP1, SRP0): Prevents modification of the Status Register until a power cycle.
    ️· One-Time Programmable Protection (SRP1, SRP0): Prevents any future modification of the Status Register.
    ️· Security Registers (LB3-LB1): Locked using the LB bits. Once locked, they become read-only.

    4. Key Commands/Operations and their Impact

    ️· Write Status Register (WRSR): Used to modify Status Register bits (except WIP and WEL).
    ️· Program/Erase Suspend (75H): Sets the SUS1 bit.
    ️· Program/Erase Resume (7AH): Clears SUS1 and SUS2 bits.