# TOSHIBA NAND memory Toggle DDR1.0 Technical Data Sheet

## 1. Introduction

️· General Description: Toggle DDR NAND provides high-speed data transfer using a bidirectional DQS signal, compatible with SDR NAND, and saves power. Supports up to 100 MHz interface speed.
️· Definitions and Abbreviations: Includes common NAND terminology (SDR, DDR, address, column, row, page, block, plane, LUN, target, status register).
️· Features:
- Organization: Provides table for device capacity, page size, block size, plane size, LUNs/targets, and valid blocks for TC58TEG6DCJ, TH58TEG7DCJ, and TH58TEG8DCJ.
- Modes: Supports basic, extend, and interleaving operation modes (depending on the model).
- Access Time: Cell array to register 100µs (max), Data Transfer rate 100MHz
- Program/Erase time: Auto Page Program 1700 µ s/page typ., Auto Block Erase 5 ms/block typ.

## 2. Physical Interface

️· Pin Descriptions: Table listing pin functions (DQ, CLE, ALE, CE, RE, WE, WP, R/B, DQS, VCC, VSS, NC, NU).
️· Pin Assignment: Top view diagram illustrating pin assignments for various models.
️· Block Diagram: Diagrams showcasing the internal architecture of TC58TEG6DCJ, TH58TEG7DCJ, and TH58TEG8DCJ.