| データシートサーチシステム |
|
The question interval is too short.
Please try again in a few seconds.
Hello, Please ask a question about 24AA128 Datasheet
# Example questions:
➢ What is the primary function of the 'wp' pin and how is it controlled?
➢ What is the role of the 'acknowledge' signal in data transfer, and how does the master device signal the end of data?
➢ Explain the difference between a 'start' and 'stop' condition on the i2c bus as described in the datasheet.
1. Device Overview & Types
️· Device Family: 24XX128 (includes 24AA128, 24LC128, and 24FC128) – These are EEPROMs (Electrically Erasable Programmable Read-Only Memories).
️· Memory Size: 128 Kbits (16 KB)
️· Interface: 2-wire serial bus (I²C compatible)
️· Package Options: PDIP, SOIC, TSSOP, MSOP, DFN, TDFN. (MSOP has limited functionality, specifically only A0/A1)
2. Pin Descriptions
️· A0, A1, A2: Chip Select inputs. Used for multiple device operation on the same bus. Must be driven high or low.
️· SDA: Serial Data - Bidirectional. Requires a pull-up resistor.
️· SCL: Serial Clock - Input.
️· WP: Write Protect - Must be connected to VSS (ground) for writes to be enabled, or to VCC to inhibit writes.
️· VCC: Power supply voltage (+1.7V to 5.5V for 24AA128, +2.5V to 5.5V for 24LC128, +1.7V to 5.5V for 24FC128).
️· VSS: Ground.
3. Functional Description / Bus Protocol
️· I²C Compatible: Uses the standard I²C protocol.
️· Master/Slave Relationship: One device acts as the "master" controlling the bus and generating timing signals. The EEPROMs act as "slaves."
️· Bus States:
- Not Busy: Both SDA and SCL high.
- Start: SDA goes low while SCL is high.
- Stop: SDA goes high while SCL is high.
- Data Valid: Data is stable during the high period of the SCL.
️· Acknowledge (ACK): A signal sent by the receiving device after each byte to confirm reception. The slave generates the acknowledge. The master sends the acknowledge signal.
4. Key Characteristics/Notes
️· MSOP Limitation: The MSOP package only supports A0 and A1 chip select lines. The others are not connected and should be driven externally.
️· Pull-Up Resistor: SDA requires a pull-up resistor.
️· Write Protection: WP pin must be connected to VSS or VCC to enable/disable writes.
️· Acknowledge Timing: Requires acknowledgement timing to be considered
️· End of Data: Master must NOT acknowledge on the final byte to signal to the slave to release the bus.
️· Endurance: 1,000,000 cycles.
This summary should give you a good overview of the key features and how to use the 24AA128/24LC128/24FC128 EEPROMs.
1. Device Overview & Types
️· Device Family: 24XX128 (includes 24AA128, 24LC128, and 24FC128) – These are EEPROMs (Electrically Erasable Programmable Read-Only Memories).
️· Memory Size: 128 Kbits (16 KB)
️· Interface: 2-wire serial bus (I²C compatible)
️· Package Options: PDIP, SOIC, TSSOP, MSOP, DFN, TDFN. (MSOP has limited functionality, specifically only A0/A1)
2. Pin Descriptions
️· A0, A1, A2: Chip Select inputs. Used for multiple device operation on the same bus. Must be driven high or low.
️· SDA: Serial Data - Bidirectional. Requires a pull-up resistor.
️· SCL: Serial Clock - Input.
️· WP: Write Protect - Must be connected to VSS (ground) for writes to be enabled, or to VCC to inhibit writes.
️· VCC: Power supply voltage (+1.7V to 5.5V for 24AA128, +2.5V to 5.5V for 24LC128, +1.7V to 5.5V for 24FC128).
️· VSS: Ground.
3. Functional Description / Bus Protocol
️· I²C Compatible: Uses the standard I²C protocol.
️· Master/Slave Relationship: One device acts as the "master" controlling the bus and generating timing signals. The EEPROMs act as "slaves."
️· Bus States:
- Not Busy: Both SDA and SCL high.
- Start: SDA goes low while SCL is high.
- Stop: SDA goes high while SCL is high.
- Data Valid: Data is stable during the high period of the SCL.
️· Acknowledge (ACK): A signal sent by the receiving device after each byte to confirm reception. The slave generates the acknowledge. The master sends the acknowledge signal.
4. Key Characteristics/Notes
️· MSOP Limitation: The MSOP package only supports A0 and A1 chip select lines. The others are not connected and should be driven externally.
️· Pull-Up Resistor: SDA requires a pull-up resistor.
️· Write Protection: WP pin must be connected to VSS or VCC to enable/disable writes.
️· Acknowledge Timing: Requires acknowledgement timing to be considered
️· End of Data: Master must NOT acknowledge on the final byte to signal to the slave to release the bus.
️· Endurance: 1,000,000 cycles.
This summary should give you a good overview of the key features and how to use the 24AA128/24LC128/24FC128 EEPROMs.
| Part No. | 24AA128 |
| Manufacturer | MICROCHIP |
| Size | 952 Kbytes |
| Pages | 38 pages |
| Description | 128K I2C??CMOS Serial EEPROM |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |