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Hello, Please ask a question about AD9626BCPZ-170 Datasheet
# Example questions:
➢ What is the typical input common-mode range for the clock inputs of the ad9626, and what is the minimum acceptable differential input voltage?
➢ What are the three logic output coding options available for the ad9626?
➢ What is the typical high-level output voltage (voh) and the maximum low-level output voltage (vol) for the ad9626?
1. Overall Context
️· Device: AD9626 (High-Speed ADC)
️· Test Conditions (General):
- AVDD = 1.8V (Analog Power)
- DRVDD = 1.8V (Digital Power)
- TMIN = -40°C (Minimum Operating Temperature)
- TMAX = +85°C (Maximum Operating Temperature)
- fIN = -1.0 dBFS (Input Signal Level)
- full scale = 1.25 V (Full Scale Range)
- DCS enabled (Digital Control System)
️· Reference Document: AN-835, _Understanding High Speed ADC Testing and Evaluation_ (provides definitions and testing methodology).
2. AC Specifications (Analog and Digital Signals)
The provided tables detail specifications for various input and output signals. Here's a summary of key parameters, grouped by signal type. Note that "Full" likely refers to a standard condition; specific AD9626 variants (AD9626-170, AD9626-210, AD9626-250) have slightly different values (as indicated in the tables) which would require referring to the full datasheet for exact numbers.
A. Clock Inputs:
️· Logic Compliance: CMOS/LVDS/LVPECL (multiple logic levels supported)
️· Internal Common-Mode Bias: 1.2V
️· Differential Input Voltage: 0.2V
️· Input Voltage Range: AVDD - 6 to AVDD + 0.3V
️· Input Common-Mode Range: 1.2 to AVDD
️· High Level Input Voltage (VIH): 1.6V
️· Low Level Input Voltage (VIL): 1.1V
️· Input Resistance (Differential): 3.6 kΩ
️· Input Capacitance: 4 pF
B. Logic Inputs (SDIO, SCLK, PDWN, CSB, RESET):
️· Logic 1 Voltage: 0.8 * AVDD
️· Logic 0 Voltage: 0.2 * AVDD
️· Logic 1 Input Current (SDIO): -60 μA
️· Logic 0 Input Current (SDIO): 55 μA
️· Input Capacitance: 4 pF
C. Logic Outputs (Data Outputs):
️· High Level Output Voltage: DRVDD - 0.05 V
️· Low Level Output Voltage: GND + 0.05 V
️· Output Coding: Twos complement, Gray code, or offset binary (default). LVDS R TERMINATION = 100 Ω.
3. Digital Specifications (Detailed)
| Parameter | Unit | Value (Typical) | Notes |
|---|---|---|---|
| Analog Power | |||
| VDD | V | 1.8 | |
| Digital Power | |||
| DRVDD | V | 1.8 | |
| Logic Inputs | |||
| Logic 1 Voltage | V | 0.8 * AVDD | |
| Logic 0 Voltage | V | 0.2 * AVDD | |
| Logic Outputs | |||
| High Level Output Voltage | V | DRVDD - 0.05 | |
| Low Level Output Voltage | V | GND + 0.05 |
1. Overall Context
️· Device: AD9626 (High-Speed ADC)
️· Test Conditions (General):
- AVDD = 1.8V (Analog Power)
- DRVDD = 1.8V (Digital Power)
- TMIN = -40°C (Minimum Operating Temperature)
- TMAX = +85°C (Maximum Operating Temperature)
- fIN = -1.0 dBFS (Input Signal Level)
- full scale = 1.25 V (Full Scale Range)
- DCS enabled (Digital Control System)
️· Reference Document: AN-835, _Understanding High Speed ADC Testing and Evaluation_ (provides definitions and testing methodology).
2. AC Specifications (Analog and Digital Signals)
The provided tables detail specifications for various input and output signals. Here's a summary of key parameters, grouped by signal type. Note that "Full" likely refers to a standard condition; specific AD9626 variants (AD9626-170, AD9626-210, AD9626-250) have slightly different values (as indicated in the tables) which would require referring to the full datasheet for exact numbers.
A. Clock Inputs:
️· Logic Compliance: CMOS/LVDS/LVPECL (multiple logic levels supported)
️· Internal Common-Mode Bias: 1.2V
️· Differential Input Voltage: 0.2V
️· Input Voltage Range: AVDD - 6 to AVDD + 0.3V
️· Input Common-Mode Range: 1.2 to AVDD
️· High Level Input Voltage (VIH): 1.6V
️· Low Level Input Voltage (VIL): 1.1V
️· Input Resistance (Differential): 3.6 kΩ
️· Input Capacitance: 4 pF
B. Logic Inputs (SDIO, SCLK, PDWN, CSB, RESET):
️· Logic 1 Voltage: 0.8 * AVDD
️· Logic 0 Voltage: 0.2 * AVDD
️· Logic 1 Input Current (SDIO): -60 μA
️· Logic 0 Input Current (SDIO): 55 μA
️· Input Capacitance: 4 pF
C. Logic Outputs (Data Outputs):
️· High Level Output Voltage: DRVDD - 0.05 V
️· Low Level Output Voltage: GND + 0.05 V
️· Output Coding: Twos complement, Gray code, or offset binary (default). LVDS R TERMINATION = 100 Ω.
3. Digital Specifications (Detailed)
| Parameter | Unit | Value (Typical) | Notes |
|---|---|---|---|
| Analog Power | |||
| VDD | V | 1.8 | |
| Digital Power | |||
| DRVDD | V | 1.8 | |
| Logic Inputs | |||
| Logic 1 Voltage | V | 0.8 * AVDD | |
| Logic 0 Voltage | V | 0.2 * AVDD | |
| Logic Outputs | |||
| High Level Output Voltage | V | DRVDD - 0.05 | |
| Low Level Output Voltage | V | GND + 0.05 |
| Part No. | AD9626BCPZ-170 |
| Manufacturer | AD |
| Size | 1Mb |
| Pages | 37 pages |
| Description | 1.8 V Analog-to-Digital Converter |
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