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74AUP1G04GW-Q100 データシート (PDF) - Nexperia B.V. All rights reserved

74AUP1G04GW-Q100 Datasheet PDF - Nexperia B.V. All rights reserved
部品番号 74AUP1G04GW-Q100
ダウンロード  74AUP1G04GW-Q100 ダウンロード
ファイルサイズ   260.81 Kbytes
ページ   16 Pages
メーカー  NEXPERIA [Nexperia B.V. All rights reserved]
ホームページ  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
部品情報 Low-power inverter

74AUP1G04GW-Q100 Datasheet (PDF)

Go To PDF Page ダウンロード データシート
74AUP1G04GW-Q100 Datasheet PDF - Nexperia B.V. All rights reserved

部品番号 74AUP1G04GW-Q100
ダウンロード  74AUP1G04GW-Q100 Click to download

ファイルサイズ   260.81 Kbytes
ページ   16 Pages
メーカー  NEXPERIA [Nexperia B.V. All rights reserved]
ホームページ  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
部品情報 Low-power inverter

74AUP1G04GW-Q100 データシート (HTML) - Nexperia B.V. All rights reserved


74AUP1G04GW-Q100 製品詳細

1. General description
The 74AUP1G04-Q100 is a single inverter.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times
across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range
from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• Low static power consumption; ICC = 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78B Class II
• Overvoltage tolerant inputs to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial Power-down mode operation
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V




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