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ST72F324J2T6 データシート(PDF) 117 Page - STMicroelectronics

部品番号 ST72F324J2T6
部品情報  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
PDF  156 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F324J2T6 データシート(HTML) 117 Page - STMicroelectronics

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12.3.4 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating condition for VDD, fCPU, and TA.
1. Data based on characterization results, not tested in production.
2. Applicable only in low voltage devices (planned).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(AVD)
1
⇒0 AVDF flag toggle threshold
(VDD rise)
VD level = High in option byte
4.41)
4.6
4.9
V
VD level = Med. in option byte2)
VD level = Low in option byte2)
3.95 1)
3.4 1)
4.15
3.6
4.4
3.8
VIT-(AVD)
0
⇒1 AVDF flag toggle threshold
(VDD fall)
VD level = High in option byte
4.2
4.4
4.65 1)
VD level = Med. in option byte2)
VD level = Low in option byte2)
3.75
3.2
4.0
3.4
4.2 1)
3.6 1)
Vhys(AVD)
AVD voltage threshold hysteresis
VIT+(AVD)-VIT-(AVD)
200
mV
∆V
IT-
Voltage drop between AVD flag set
and LVD reset activated
VIT-(AVD)-VIT-(LVD)
450
mV



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