¡ Semiconductor

MSM6926/6946

5/25

Control

LT

444I

on the RD pin, and any data sent on the RS1 pin will immediately appear on the

modulated data to implement the transmitted carrier. In this case, sending the

transmitted carrier to the phone line depends on the CC, but never on RS1.

During digital loop back test, the data on this pin becomes a control signal for sending

the transmitted carrier to the phone line in place of RS1.

CC

52I

When an external circuit gives the RS/CS delay time which is not within the device

as required, this pin should be connected to the external circuit output.

See Fig. 11.

RS2

88I

The fast carrier detection output. This pin is internally connected to the input of

the built-in carrier detect delay circuit. When an external delay circuit provides

the delay time which is not within the device as required, the CD1 should be

connected to the external circuit input. See Fig. 11.

CD1

11

12

O

Name

Pin No.

RS GS-K

I/O

Description

CD2

12

13

I/O

When an external circuit gives the carrier detect delay time which is not within

the device as required, this pin becomes the input pin for the external circuit

output signal. In other cases (when using the delay time within the device, the

data on the TS1 or TS2 is not digital "High"), this pin becomes the Carrier detect

signal output.

The RD1 data is demodulated data from the received carrier and the RD2 is the

input of the following logic circuits referred to in Fig. 12. Usually, the RD1 data

is input directly to RD2. In some cases, as input data to RD2, the data that is

controlled by NCU (Network control unit) etc. may be required in stead of the

RD1 data.

RD1

13

14

O

RD2

14

16

I

These two pins are the output (CRD1) and inverting input (CDR2) of the buffer

operational amplifier of which the noninverting input is connected to the built-in

voltage reference, stabilized to variations in the supply voltage and temperature.

See Fig. 13. An adequate carrier-detect level can be set by selecting the ratio of

should be greater than 50 k

W.

CDR1

16

20

O

CDR2

17

21

I

Answer/Originate mode select. During digital "High", the originate mode is

selected. A low input selects the answer mode.

M22

31

I

be connected to receiving filter output instead of transmitting filter output.

FT

23

32

I

RS/CS delay and carrier detect delay options referred to chapter about timing

characteristics are selected by TS1 and TS2 inputs. Be careful that each delay

can not be individually selected. If another delay time than the ones within the

device are required as an option, input a digital "High" to the TS1 and TS2 pin

and implement the external delay circuits to obtain the desired delay

characteristics. In this case, the CD2 pin becomes not only the input for the

external circuit output signal, but also the Carrier detect output. See Fig. 11.

TS1

27

36

I

TS2

28

38

I