STR720 datasheet(396/401 Pages) STMICROELECTRONICS

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STR720 - ELECTRICAL CHARACTERISTICS

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28.13 SDRAM Interface Timing

The signals composing SDRAM interface are collected on Port 6 and as such all their DC

electrical characteristics are reported in Table 99. The following tables and figures report the

timing characteristics of read and write cycles, both as single and burst accesses.

Figure 84. EMI Write cycle timing (32-bit word)

Table 110. SDRAM Read cycle timing characteristics

Symbol

Parameter(1)

Test Conditions(2)

Value(4)

Unit

Min

Typ

Max

tSCH

SDRAM clock high pulse time

0.5TC

-ns

tSCL

SDRAM clock low pulse time

0.5TC

-ns

tSCAD

SDRAM clock high to address

valid

tSCCS

SDRAM clock high to chip select

tSCRA

SDRAM clock high to RAS

tSCCA

SDRAM clock high to CAS

tSCWE

SDRAM clock high to WE

tSDS

SDRAM Data read setup(3)

tSDH

SDRAM Data read hold(3)

tSCDA

SDRAM clock high to data valid

tSCBL

SDRAM clock high to BLS

tSCCKE

SDRAM clock high to CKEN

tSRACA

SDRAM RAS to CAS delay(3)

Depends on SDRAM config-

uration.(5)

-8TC

wait cycle

ECSx

ERD

EADD[21:1]

Address

wait cycle

tWASC

tWAH

Note: this diagram shows the timing of 1 wait-state cycle write access.

tWPW1

EWEx

EDATA[15:0]

(Output)

Data Output

tWDH

tWASW

tWASD

tWPC2

EADD[0]

Data Output

tWPW1

tWDH

tWWT

tWPC1

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