ST7232A datasheet(121/154 Pages) STMICROELECTRONICS

部品番号	ST7232A

部品情報	8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE

PDF	154 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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ST7232A

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CLOCK CHARACTERISTICS (Cont’d)

12.5.4 PLL Characteristics

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or

sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 64 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 64. Integrated PLL Jitter vs signal frequency1

Note 1: Measurement conditions: fCPU = 8MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fOSC

PLL input frequency range

MHz

∆ fCPU/ fCPU Instantaneous PLL jitter 1)

fOSC = 4 MHz.

0.7

0.2

0.4

0.6

0.8

1.2

4 MHz

2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

+/-Jitter (%)

max

typ

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