AM652X datasheet(179/282 Pages) TI1

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•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX_100:

•

gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

7.9.5.10.1.2 GPMC and NOR Flash Switching Characteristics—Synchronous Mode

NO.(2) PARAMETER

DESCRIPTION

MODE(19)

MIN

MAX UNIT

tc(clk)

Period, output clock GPMC_CLK (18)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

tw(clkH)

Typical pulse duration, output clock GPMC_CLK

high

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-0.3+0.4

75*P (15)

tw(clkL)

Typical pulse duration, output clock GPMC_CLK

low

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-0.3+0.4

75*P (15)

td(clkH-csnV)

Delay time, output clock GPMC_CLK rising edge to

output chip select GPMC_CSn[x] transition (14)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+F (6) 4.5+F (6)

td(clkH-csnIV)

Delay time, output clock GPMC_CLK rising edge to

output chip select GPMC_CSn[x] invalid (14)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+E

(5)

4.5+E (5)

td(aV-clk)

Delay time, output address GPMC_A[27:1] valid to

output clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

4.5+B (2)

td(clkH-aIV)

Delay time, output clock GPMC_CLK rising edge to

output address GPMC_A[27:1] invalid

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3

4.5

td(be[x]nV-clk)

Delay time, output lower byte enable and

command latch enable GPMC_BE0n_CLE, output

upper byte enable GPMC_BE1n valid to output

clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

1.9+B (2)

td(clkH-be[x]nIV)

Delay time, output clock GPMC_CLK rising edge

to output lower byte enable and command latch

enable GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n invalid (11)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D (4)

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge to

GPMC_BE0n_CLE, GPMC_BE1n invalid (12)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D (4)

td(clkL-be[x]nIV).

Delay time, GPMC_CLK falling edge to

GPMC_BE0n_CLE, GPMC_BE1n invalid (13)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D (4)

td(clkH-advn)

Delay time, output clock GPMC_CLK rising edge

to output address valid and address latch enable

GPMC_ADVn_ALE transition

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+G

(7)

4.5+G (7)

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AM6548, AM6528, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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