BTN8962 datasheet(66/94 Pages) INFINEON

部品番号	BTN8962

部品情報	High Current PN Half Bridge

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To determine the delay for a rising edge tr(HS),total, the voltage limit is set to the corresponding current level,

which is reached with a voltage drop of 80% of VOUT ≈ VS over the test resistor Rtest, as shown in the test setup in

Figure 70. As this test is based on the concurrency of the output voltage and current IL, only an ohmic load

should be used. This setup results in the direct proportional context of IL = VS ⁄ Rtest and with the current sense

function from Chapter 4.5:

IIS =

IL

dkILIS

+ IIS offset =

Vs

dkILIS ⋅ Rtest

+ IIS offset

Equation 25

The resulting voltage VADC on the microcontroller’s ADC input pin (according to Figure 70):

VADC = R12 ⋅ IIS =

Vs ⋅ R12

dkILIS ⋅ Rtest

+ IIS offset ⋅ R12

Equation 26

This means that the comparator threshold should be set to a corresponding voltage level of:

VADC,80%V

s

= 0.8

⋅

Vs ⋅ R12

dkILIS ⋅ Rtest

+ IIS offset ⋅ R12

Equation 27

This procedure allows to measure the input delay tr(HS),total with a microcontroller’s ADC in a predefined end of

line test, with a known resistor Rtest. The test is summarized in Figure 71. The time measurement is started in

parallel to the rising edge of the IN input pin. If the voltage level of VADC, as described in Equation 27, is reached,

the resulting delay time tr(HS),total can be calculated.

BTN8960 /62 /80 /82

High Current PN Half Bridge

Switching Timing

Application Note

66

Rev. 0.6

2017-02-21

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