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BTN8962 データシート(PDF) 9 Page - Infineon Technologies AG |
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BTN8962 データシート(HTML) 9 Page - Infineon Technologies AG |
9 / 94 page 3 Design Guideline For a safe and sufficient motor control design, discrete components are needed. Some of them must be dedicated to the motor application and some to the NovalithIC™. 3.1 Schematic and layout design rules Figure 5 and Figure 6 show an example of a schematic plus a corresponding layout for a half-bridge motor control with NovalithIC™. The best performance in terms of parasitic inductance and EMC can be reached with a GND plane, which we strongly recommend be used. Figure 5 Example of a half-bridge schematic with NovalithICTM Important design and layout rules: The basis for the following items is the parasitic inductance of electrical wires, as described in Chapter 2. • C10, so called DC-link capacitor: This electrolytic capacitor is required to keep the voltage ripple at the VS- pin of the NovalithIC™ low during switching operation (the measurement procedure for the supply voltage is described in Chapter 2.1). It is strongly recommended that the voltage ripple at the NovalithIC™Vs-pin to GND-pin be kept below 1 V peak-to-peak. The value of C10 must be aligned accordingly. See Equation 10. Most electrolytic capacitors are less effective at cold temperatures. It must be assured that C10 is also effective under the worst case conditions of the application. The layout is very important. As shown in Figure 6, the capacitor C10 must be positioned with very short wiring at the NovalithIC™. This must be done to keep the parasitic inductors of the PCB-wires as small as possible. • C9: This ceramic capacitor supports C10 to keep the supply voltage ripple low and covers the fast transients between the Vs-pin and the GND-pin. The value of this ceramic capacitor must be chosen so that fast Vs- ripple at the NovalithIC™ does not exceed 1 V peak-to-peak. The layout wiring for C9 must be shorter than for C10 to the NovalithIC™ to keep the parasitic PCB-wire inductance as small as possible. In addition the parasitic inductance could be kept low by placing at least two vias for the connection to the GND-layer. • C_O2V: This ceramic capacitor is important for EMI in order to avoid entering electromagnetic disturbances into the NovalithIC™ as much as possible. Good results have been achieved with a value of 220 nF. In terms of layout, it is important to place this capacitor between “OUT” and “Vs” without significant additional wiring from C_O2V to the Vs- and OUT-line. • C_OUT: This ceramic capacitor helps improve the EMI and the ESD performance of the application. Good results have been achieved with a value of 220 nF. To keep the RF and ESD out of the board, the capacitor is most effective when positioned directly on the board connector. In addition, the parasitic inductance could be kept low by placing at least two vias for the connection to the GND-layer. • C1: This ceramic capacitor helps to improve the EMI and the ESD performance. In combination with L1 and C10 plus C9 a Pi-filter improves the electromagnetic emission on the Vs-line. Layout rules are the same as for C_OUT. BTN8960 /62 /80 /82 High Current PN Half Bridge Design Guideline Application Note 9 Rev. 0.6 2017-02-21 |
同様の部品番号 - BTN8962 |
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同様の説明 - BTN8962 |
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