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KSZ9567RTXI-TR データシート(PDF) 179 Page - Microchip Technology |
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KSZ9567RTXI-TR データシート(HTML) 179 Page - Microchip Technology |
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179 / 232 page  2017-2019 Microchip Technology Inc. DS00002329D-page 179 KSZ9567R 5.2.8.5 Port Transmit Credit Shaper Control 0 Register This register is indexed. Settings are applied on a per-queue and per-port basis. Specify the target queue number in the Port Transmit Queue Index Register before accessing this register. 5.2.8.6 Port Transmit Credit Shaper Control 1 Register This register is indexed. Settings are applied on a per-queue and per-port basis. Specify the target queue number in the Port Transmit Queue Index Register before accessing this register. 5.2.8.7 Port Transmit Credit Shaper Control 2 Register This register is indexed. Settings are applied on a per-queue and per-port basis. Specify the target queue number in the Port Transmit Queue Index Register before accessing this register. Address: 0xN916 - 0xN917 Port N: 1- Size: 16 bits Bits Description Type Default 15:0 Port Queue Credit High Water Mark Shaper credit high water mark in bytes R/W 0x0534 Address: 0xN918 - 0xN919 Port N: 1- Size: 16 bits Bits Description Type Default 15:0 Port Queue Credit Low Water Mark Shaper credit low water mark in bytes R/W 0x05F2 Address: 0xN91A - 0xN91B Port N: 1- Size: 16 bits Bits Description Type Default 15:0 Port Queue Credit Increment Shaper credit increment, 12.5% R/W 0x2000 |
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