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AM68AX データシート(PDF) 219 Page - Texas Instruments |
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AM68AX データシート(HTML) 219 Page - Texas Instruments |
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219 / 251 page  7.10.5.19.1 OSPI0 PHY Mode 7.10.5.19.1.1 OSPI With Data Training Note I/O timing requirements and switching characteristics are not applicable when OSPI is used with data training. Follow the OSPI and QSPI Board Design and Layout Guidelines section to ensure proper operation. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training PARAMETER DESCRIPTION MODE MIN MAX UNIT tc(CLK) Cycle time, CLK DDR, 1.8V 6 ns DDR, 3.3V 7.5 ns tc(CLK) Cycle time, CLK SDR, 1.8V 6 ns SDR, 3.3V 7.5 ns 7.10.5.19.1.2 OSPI Without Data Training Note The I/O Timings provided in this section are only applicable when data training is not implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL Delays are configured as described in Table 7-82 found in this section. Section 7.10.5.19.1.2.4, Section 7.10.5.19.1.2.2, Section 7.10.5.19.1.2, and Section 7.10.5.19.1.2 present switching characteristics for OSPI DDR and SDR Mode. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode Table 7-82. OSPI DLL Delay Mapping - SDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE All modes PHY_CONFIG_TX_DLL_DELAY_FLD 0x0 PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 Table 7-83. OSPI Timing Requirements – SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O21 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK input (DQS) edge(1) 1.8V, External Board Loopback 0.6 ns 3.3V, External Board Loopback 0.9 ns O22 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK input (DQS) edge(1) 1.8V, External Board Loopback 1.7 ns 3.3V, External Board Loopback 2 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 OSPI_DQS OSPI_TIMING_06 O21 O 2 2 OSPI_D[i:0] Figure 7-98. OSPI Timing Requirements – SDR, External Loopback Clock www.ti.com AM68A SPRSP91 – FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: AM68A |
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