HC705JJ7GRSSLASHD datasheet(145/230 Pages) NXP

部品番号	HC705JJ7GRS/D

部品情報	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

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メーカー	NXP [NXP Semiconductors]

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Simple Serial Interface

SIOP Registers

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Simple Serial Interface

9.4.3 SIOP Data Register (SDR)

The SIOP data register (SDR) is located at address $000C and serves

as both the transmit and receive data register. Writing to this register will

initiate a message transmission if the node is in master mode. The SIOP

subsystem is not double buffered and any write to this register will

destroy the previous contents. The SDR can be read at any time.

However, if a transfer is in progress the results may be ambiguous.

Writing to the SDR while a transfer is in progress can cause invalid data

to be transmitted and/or received. Figure 9-6 shows the position of each

bit in the register. This register is not affected by reset.

$000C

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

Unaffected by Reset

Figure 9-6. SIOP Data Register (SDR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D データシート(PDF) 145 Page - NXP Semiconductors