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HC705JJ7GRS/D データシート(PDF) 160 Page - NXP Semiconductors |
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HC705JJ7GRS/D データシート(HTML) 160 Page - NXP Semiconductors |
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160 / 230 page  Programmable Timer General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Programmable Timer NOTE: To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL. 11.4 Alternate Counter Registers (ACRH and ACRL) The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 11-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF flag bit and timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter. Figure 11-4. Alternate Counter Block Diagram The alternate counter registers (ACRH and ACRL) shown in Figure 11-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC. ACRH ($001A) TMR LSB 16-BIT COUNTER ÷ 4 INTERNAL (OSC ÷ 2) RESET CLOCK ACRL ($001B) INTERNAL ($FFFC) DATA READ ACRH READ ACRL READ LATCH BUS Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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