QB-R5F100SL-TB datasheet(161/207 Pages) RENESAS

部品番号	QB-R5F100SL-TB

部品情報	True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz

PDF	207 Pages

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メーカー	RENESAS [Renesas Technology Corp]

ホームページ	http://www.renesas.com

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161 / 207 page

RL78/G13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0131EJ0350 Rev.3.50

161 of 200

Jun 30, 2020

Simplified I2C mode connection diagram (during communication at different potential)

SDAr

SCLr

SDA

SCL

User device

RL78

microcontroller

Simplified I2C mode serial transfer timing (during communication at different potential)

SDAr

tLOW

tHIGH

tHD:DAT

SCLr

tSU:DAT

1/fSCL

Caution

Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch open

drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin

products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode

Remarks 1. Rb[

Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load

capacitance, Vb[V]: Communication line voltage

2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 01, 02, 10, 12, 13)

QB-R5F100SL-TB データシート(PDF) 161 Page - Renesas Technology Corp