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STM32U595AI データシート(PDF) 301 Page - STMicroelectronics

部品番号 STM32U595AI
部品情報  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, up to 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI
PDF  377 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
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STM32U595AI データシート(HTML) 301 Page - STMicroelectronics

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DS13633 Rev 1
301/377
STM32U59xxx
Electrical characteristics
343
5.3.31
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 32, with the following configuration:
•
LCD_CLK polarity: high
•
LCD_DE polarity: low
•
LCD_VSYNC and LCD_HSYNC polarity: high
•
Pixel formats: 24 bits
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Table 114. LTDC characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fCLK
LTDC clock output
frequency
2.7 V ≤ VDD ≤ 3.6 V, CL = 20 pF
-
116
MHz
2.7 V ≤ VDD ≤ 3.6 V
100
1.71 V ≤ VDD ≤ 3.6 V
66.5
DCLK
LTDC clock output duty cycle
45
55
%
tW(CLKH)
tW(CLKL)
Clock High time, low time
tW(CLK)/2 - 0.5
tW(CLK)/2 + 0.5
ns
tV(DATA)
Data output valid
time
2.7 V ≤ VDD ≤ 3.6 V
-
2.5
1.71 V ≤ VDD ≤ 3.6 V
7.5
tH(DATA)
Data output hold time
0.5
-
tV(HSYNC)
tV(VSYNC)
tV(DE)
HSYNC/VSYNC/DE output valid time
-
3
tH(HSYNC)
tH(VSYNC)
tH(DE)
HSYNC/VSYNC/DE output hold time
1.5
-
1. Evaluated by characterization. Not tested in production.



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