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STM32H7B3AI データシート(PDF) 129 Page - STMicroelectronics

部品番号 STM32H7B3AI
部品情報  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3AI データシート(HTML) 129 Page - STMicroelectronics

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Table 79. Asynchronous multiplexed PSRAM/NOR write - NWAIT timings
Symbol
Parameter
Min(1)
Max(1)
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck − 1
9Tfmc_ker_ck
ns
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck − 0.5
7Tfmc_ker_ck + 0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5Tfmc_ker_ck + 9
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
4Tfmc_ker_ck + 12
-
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 39 through Figure 42 represent synchronous waveforms and Table 80 through Table 83 provide the
corresponding timings. The results shown in these tables are obtained with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM
In all timing tables, Tfmc_ker_ck is the kernel clock period, with the following FMC_CLK maximum values:
•
For 2.7 V < VDD < 3.6 V, FMC_CLK = 125 MHz at 20 pF
•
For 1.8 V < VDD < 1.9 V, FMC_CLK = 100 MHz at 20 pF
•
For 1.62 V < VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 129/238



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