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STM32H7B3AI データシート(PDF) 177 Page - STMicroelectronics |
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STM32H7B3AI データシート(HTML) 177 Page - STMicroelectronics |
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177 / 238 page  Figure 73. SAI master timing waveforms SAI_SCK_X SAI_FS_X(output) 1/fSCK SAI_SD_X(transmit) tv(FS) Slot n SAI_SD_X(receive) th(FS) Slot n+2 tv(SD_MT) th(SD_MT) Slot n tsu(SD_MR) th(SD_MR) Figure 74. SAI slave timing waveforms SAI_SCK_X SAI_FS_X(input) SAI_SD_X(transmit) tsu(FS) Slot n SAI_SD_X(receive) tw(CKH_X) th(FS) Slot n+2 tv(SD_ST) th(SD_ST) Slot n tsu(SD_SR) tw(CKL_X) th(SD_SR) 1/fSCK 6.3.36.6 MDIO characteristics Unless otherwise specified, the parameters given in Table 121 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 22. General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Measurement points are done at CMOS levels: 0.5VDD • I/O compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 Note: At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable. STM32H7B3xI Operating conditions DS13139 - Rev 8 page 177/238 |
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