STM32U545NET3QTR datasheet(201/283 Pages) STMICROELECTRONICS

201 / 283 page

DS14216 Rev 1

201/283

STM32U545xx

Electrical characteristics

258

tLOCK(3)(4) PLL lock time

Integer mode

μs

Fractional mode

Jitter

RMS cycle-to-

cycle jitter

Integer mode, VCO = 544 MHz

±ps

Fractional mode, VCO = 544 MHz

RMS period jitter

Integer mode, VCO = 544 MHz

Fractional mode, VCO = 544 MHz

Long-term

jitter(5),

fPLL_IN = 8 MHz

Integer mode, VCO = 544 MHz

160

Fractional mode, VCO = 544 MHz

170

IDD(PLL)

PLL power

consumption on

VDD

with LDO

VCO freq = 160 MHz,

1 clock output

Range 1

370

μA

VCO freq = 160 MHz,

3 clock outputs

Range 1

390

VCO freq = 200 MHz,

1 clock output

Range 1

460

Range 2

435

Range 3

410

VCO freq = 336 MHz,

1 clock output

Range 1

710

VCO freq = 544 MHz,

1 clock output

Range 1

1100

IDD(PLL)

PLL power

consumption on

VDD

with SMPS

VCO freq = 160 MHz,

1 clock output

Range 1, IVCORE(6) = 19.4 mA

260

VCO freq = 160 MHz,

3 clock outputs

Range 1, IVCORE(6) = 19.4 mA

270

VCO freq = 200 MHz,

1 clock output

Range 1, IVCORE(6) = 19.4 mA

320

Range 2, IVCORE(6) = 11.7 mA

300

Range 3, IVCORE(6) = 5.74 mA

290

VCO freq = 336 MHz,

1 clock output

Range 1, IVCORE(6) = 19.4 mA

470

VCO freq = 544 MHz,

1 clock output

Range 1, IVCORE(6) = 19.4 mA

730

1. Specified by design and not tested in production, unless otherwise specified.

2. PLL1 output Q and PLL2 output Q can be up to 200 MHz only when selected as OCTOSPI clock.

3. Evaluated by characterization. Not tested in production.

4. Lock time is the duration until PLLxRDY flag (2% of final frequency).

5. Measured on 5000 cycles.

6. SMPS efficiency based on CoreMark RUN current on VCORE at max frequency of each voltage range.

Table 86. PLL characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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