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STM32U545NET3QTR データシート(PDF) 251 Page - STMicroelectronics |
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STM32U545NET3QTR データシート(HTML) 251 Page - STMicroelectronics |
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251 / 283 page  DS14216 Rev 1 251/283 STM32U545xx Electrical characteristics 258 Figure 52. USART timing diagram in slave mode 5.3.35 SPI characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 33. • Output speed set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). MSv65387V4 NSS input CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 TX output RX input tsu(RX) th(RX) tw(CKL) tw(CKH) 1/fCK th(NSS) tsu(NSS) tv(TX) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(TX) Last bit IN |
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