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STM32G0C1NET7 データシート(PDF) 119 Page - STMicroelectronics

部品番号 STM32G0C1NET7
部品情報  Arm® Cortex®-M0 32-bit MCU, up to 512KB Flash, 144KB RAM,6x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V
PDF  159 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G0C1NET7 データシート(HTML) 119 Page - STMicroelectronics

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DS13564 Rev 4
119/159
STM32G0C1xC/xE
Electrical characteristics
124
Figure 31. SPI timing diagram - slave mode and CPHA = 0
Figure 32. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
th(SO)
Slave data output hold
time
-5
-
-
ns
th(MO)
Master data output hold
time
-1
-
-
ns
1. Based on characterization results, not tested in production.
Table 75. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN
MSv41659V1
NSS input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tsu(NSS)
tc(SCK)
ta(SO)
tv(SO)
First bit OUT
Next bits OUT
Next bits IN
Last bit OUT
th(SO)
tr(SCK)
tf(SCK)
th(NSS)
tdis(SO)
First bit IN
Last bit IN



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