ST7L15 datasheet(129/138 Pages) STMICROELECTRONICS

129 / 138 page

ST7L15, ST7L19

129/138

OPTION BYTES (cont’d)

15.1.2 ROM Option Bytes

The 2 option bytes allow the hardware configura-

tion of the microcontroller to be selected.

OPTION BYTE 0

OPT7 = AWUCK Auto Wake Up Clock Selection

0: 32 kHz oscillator (VLP) selected as AWU clock

1: AWU RC oscillator selected as AWU clock.

Note: If this bit is reset, internal RC oscillator must

be selected (Option OSC = 0).

OPT6:4 = OSCRANGE[2:0] Oscillator Range

When the internal RC oscillator is not selected

(Option OSC = 1), these option bits select the

range of the resonator oscillator current source or

the external clock source.

Note: OSCRANGE[2:0] has no effect when

AWUCK option is set to 0. In this case, the VLP os-

cillator range is automatically selected as AWU

clock.

OPT 3:2 = Reserved (must be set to 1:1)

OPT1 = ROP_R Readout protection for ROM

This option is for read protection of ROM

0: Readout protection off

1: Readout protection on

OPT 0 = ROP_D Readout protection for Data

EEPROM

This option is for read protection of EEPROM

memory.

0: Readout protection off

1: Readout protection on

OPTION BYTE 1

OPT 7 = Reserved (must be set to 1)

OPT 6 = PLLOFF PLL Disable

This option bit enables or disables the PLL.

0: PLL enabled

1: PLL disabled (bypassed)

OPT 5 = Reserved (must be set to 0)

OPT 4 = OSC RC Oscillator Selection

This option bit is used to select the internal RC os-

cillator.

0: RC oscillator on

1: RC oscillator off

Note: If the RC oscillator is selected, then to im-

prove clock stability and frequency accuracy, it is

recommended to place a decoupling capacitor,

typically 100nF, between the VDD and VSS pins as

close as possible to the ST7 device.

OPT 3:2 = LVD[1:0] Low Voltage Selection

These option bits enable the voltage detection

block (LVD) with a selected threshold to the LVD.

OPT 1 = WDGSW Hardware or Software Watch-

dog

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT 0 = WDG HALT Watchdog Reset on Halt

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No reset generation when entering HALT mode

1: Reset generation when entering HALT mode

OSCRANGE

Typ. frequency

range with

resonator

1~2 MHz

2~4 MHz

4~8 MHz

8~16 MHz

VLP 32.768~ kHz

External clock on OSC1

Reserved

Configuration

VD1

VD0

LVD Off

LVD High Threshold

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