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DEM-ADS7843E/45E

DUT CONNECTIONS

The DEM-ADS7843E/45E DUT Board has a socket for the

DUT which is positioned in the DUT1 position. Addition-

ally, it has a solder footprint in the event that the user

chooses to solder the DUT directly to the board. This

footprint is poisitioned in X1, just below the DUT1 socket.

If the solder footprint is used, care should be taken to

preserve the solder pads for repeated soldering. Bad X1

solder pads do not interfere with the operation or connec-

tions of the DUT1 socket.

The DEM-ADS7843E/45E evaluation fixture is designed to

evaluate both the ADS7843 and ADS7845 A/D converters.

JP9 must be in position B to evaluate either the ADS7843 or

ADS7845.

Space for an R/C input filter has been provided to allow user

customization for the particular application. Shorting bars

have been installed in R3, R5, R7, R9, R10, and R12 positions

on the board. These are positioned betwen the input of the

DUT and the pin connector, P1. Shorting bars were used to

allow for immediate evaluation of a four-wire touch screen.

In this situation, the touch screen would provide the source

resistance. If resistors are desired in positions R3, R5, R7, R9,

R10, and R12, the user can solder in the desired values.

Additionally, positions for capacitors at the input of the DUT

are provided with C3, C4, C5, C6, C9 and C10. Once again, the

user must install appropriate values for the application under

evaluation.

The voltage reference to the DUT is programmed in the JP1.

The JP1 options are given in Table III.

The digital I/O pins of the DUT may be driven or monitored

with the J2 connector. The assignment of these pins are

summarized in Table V.

POSITION

RESULTING CONFIGURATION

A

1.2V is configured to pin 9 (VREF) of the DUT.

B

The power supply from J4 is configured to pin 9 (VREF)

of the DUT.

C

2.5V is configured to pin 9 (VREF) of the DUT.

TABLE III. VREF is Programmed Using JP1 Position Options.

The combination of JP2 allows jumper programmable set-

tings of the PENIRQ of the ADS7843 or ADS7845 pin of the

DUT. Additionally, this pin can be accessed through J2 and

a combination of JP10 and JP11. Refer to Table IV for

jumper position details. Refer to the ADS7845 data sheet for

additional options.

JP2 POSITION

JP10 POSITION

JP11 POSITION

RESULTING CONFIGURATION

Not Installed

Not Installed

Not Installed

Pin 11 of the DUT is HIGH.

Not Installed

Installed

Not Installed

Pin 11 of the DUT is connected to position 5 of J2. If there is no

connection to position 5 of J2, pin 11 of the DUT will default HIGH.

Not Installed

Not Installed

Installed

Pin 11 of the DUT is inverted and connected to position 5 of J2. If

there is no connection to position 5 of J2, pin 11 of the DUT will

default HIGH.

Installed

Not Installed

Not Installed

Pin 11 of the DUT is LOW.

Installed

Installed

Not Installed

Pin 11 of the DUT is connected to position 5 of J2. If there is no

connection to position 5 of J2, pin 11 of the DUT will default LOW.

Installed

Not Installed

Installed

Pin 11 of the DUT is inverted and connected to position 5 of J2. If

there is no connection to position 5 of J2, pin 11 of the DUT will

default LOW.

TABLE IV. PENIRQ (ADS7843 or ADS7845) Jumper Settings.

J2 PIN NUMBER

(From Left to Right)

ADS7843 PIN DESCRIPTION

1CS

2

DCLK

3

BUSY

4

DIN

5

PENIRQ

6

DOUT

TABLE V. J2 Connector Contacts versus DUT Pins.

(NOTE: If you have a DEM-ADS7843E/45E,

Revision A, the silkscreen is in error. The above

description is correct.)

STAND-ALONE OPERATION

The DUT can be evaluated in a stand-alone configuration by

removing all of the jumper tops of JP4. JP4 connects pins 12,

13, 14, 15, and 16 of the DUT to the digital interface

circuitry of the board. If the array of jumper tops are not

removed, the user may find significant conflicts on the

digital I/O lines of the DUT. The details of this interface

circuitry is discussed in detail in the “Digital Interface”

section of this data sheet.

DIGITAL INTERFACE CIRCUITRY

The DUT can be evaluated using the digital clocking cir-

cuitry on the board by installing all of the jumper tops of JP4

and removing any signal present on the J2 connector. This

digital circuit uses the clock signal from P1 (External Clock)

or Y1 to create the DUT clock (DCLK), CS, and the DIN

code to the device while providing a serial or parallel output

signal from the DOUT pin of the DUT.

Clock Control

The master clock to the board is set with the JP6 jumper.

Position A of the JP6 jumper configures the External Clock

(P1) coax connector into the circuit. It is recommended that

this signal be a logic square wave. The signal from this

connector will be used directly for the DCLK signal to the