AT89C5131A-RDTIL datasheet(145/185 Pages) ATMEL

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AT89C5131A-L

4338E–USB–06/06

Table 103. UEPINT Register

UEPINT (S:F8h read-only)

USB Endpoint Interrupt Register

Reset Value = 00h

EP6INT

EP5INT

EP4INT

EP3INT

EP2INT

EP1INT

EP0INT

Bit Number

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

EP6INT

Endpoint 6 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 6. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP6IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

EP5INT

Endpoint 5 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 5. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP5IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

EP4INT

Endpoint 4 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 4. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP4IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

EP3INT

Endpoint 3 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 3. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP3IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

EP2INT

Endpoint 2 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

EP1INT

Endpoint 1 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

EP0INT

Endpoint 0 Interrupt

This bit is set by hardware when an endpoint interrupt source has been detected on the

endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP,

RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are cleared

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