1

Features

– 2.7 (V

– Protect 1/4, 1/2, or Entire Array

Both Hardware and Software Data Protection

– Endurance: One Million Write Cycles

– Data Retention: 100 Years

Description

The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable

programmable read only memory (EEPROM) organized as 128/256/512 words of 8

bits each. The device is optimized for use in many industrial and commercial applica-

tions where low-power and low voltage operation are essential. The AT25010/020/040

is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages.

The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a

3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-

rate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with one of

four blocks of write protection. Separate program enable and program disable instruc-

tions are provided for additional data protection. Hardware data protection is provided

via the WP pin to protect against inadvertent write attempts. The HOLD pin may be

used to suspend any serial communication without resetting the serial sequence.

SPI Serial

EEPROMs

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

AT25010

AT25020

AT25040

Pin Configurations

Pin Name

Function

CS

Chip Select

SCK

Serial Data Clock

SI

Serial Data Input

SO

Serial Data Output

GND

Ground

VCC

Power Supply

WP

Write Protect

HOLD

Suspends Serial Input

8-lead PDIP

1

2

3

4

8

7

6

5

CS

SO

WP

GND

VCC

HOLD

SCK

SI

8-lead SOIC

1

2

3

4

8

7

6

5

CS

SO

WP

GND

VCC

HOLD

SCK

SI

Rev. 0606M–SEEPR–06/03