GSCNE555

Page: 5/5

ISSUED DATE :2005/08/10

REVISED DATE :2006/05/15C

Application Circuit

Application Notes

The application circuit shows astable mode configuration.

of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of

discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One

and RB. Therefore, flip-flop circuit is set output high.

That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is

low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is

0.693RB*C1.

In

=0.693

T1=0.693*(RA+RB)*C1

Thus the total period time T is given by

T2=0.693*RB*C1

T=T1+T2=0.693(RA+2RB)*C1

Then the frequency of astable mode is given by

f =

=

The duty cycle is given by

D.C. =

=

Important Notice:

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM.

GTM reserves the right to make changes to its products without notice.

GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems.

GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.

Head Office And Factory:

Taiwan: No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C.

TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785

China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China

TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165

FLIP-FLOP

GSCNE555

1

3

Vcc-

Vcc

2

13

Vcc-

Vcc

1

T

(RA+2RB)*C1

1.44

T2

T

RA+2RB

RB