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PIC18F4685-I/SP データシート(PDF) 116 Page - Microchip Technology |
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PIC18F4685-I/SP データシート(HTML) 116 Page - Microchip Technology |
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116 / 484 page ![]() PIC18F2682/2685/4682/4685 DS39761B-page 114 Preliminary © 2007 Microchip Technology Inc. FIGURE 9-1: INTERRUPT LOGIC TMR0IE GIE/GIEH PEIE/GIEL Wake-up if in Sleep Mode Interrupt to CPU Vector to Location 0008h INT2IF INT2IE INT2IP INT1IF INT1IE INT1IP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP IPEN TMR0IF TMR0IP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP RBIF RBIE RBIP INT0IF INT0IE PEIE/GIEL Interrupt to CPU Vector to Location IPEN IPEN 0018h Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts TMR1IF TMR1IE TMR1IP High Priority Interrupt Generation Low Priority Interrupt Generation XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts GIE/GEIH |
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