TDA4VEN...Q1 datasheet(127/236 Pages) TI

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6.9.5.2.3 CPSW3G RGMII Timing

Table 6-35, Table 6-36, Table 6-37, Figure 6-31, Table 6-38, Table 6-39, and Figure 6-32 present timing

conditions, timing requirements, and switching characteristics for CPSW3G RGMII.

Table 6-35. CPSW3G RGMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDD(1) = 1.8V

1.44

V/ns

VDD(1) = 3.3V

2.64

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

RGMII[x]_RXC,

RGMII[x]_RD[3:0],

RGMII[x]_RX_CTL

RGMII[x]_TXC,

RGMII[x]_TD[3:0],

RGMII[x]_TX_CTL

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see

POWER column of the Pin Attributes table.

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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