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TMP93CS41 データシート(PDF) 127 Page - Toshiba Semiconductor |
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TMP93CS41 データシート(HTML) 127 Page - Toshiba Semiconductor |
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127 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-125 Figure 3.8.10 is a block diagram of this mode. Figure 3.8.10 Block Diagram of PWM Timer Mode (PWM0) In this mode, enabling double buffer is very useful. The register buffer value shifts into TREG2 when a 2n − 1 overflow is detected, when double buffer is enabled. Use of the double buffer makes the handling of low duty waves easy. Figure 3.8.11 Register Buffer Operation Shift trigger φP1 φP4 φP16 P0MOD<T2CLK1:0> Clock control P0MOD<DB2EN> Selector B A TREG2 WR Register buffer 8-bit timer register (TREG2) 8-bit comparator (CP2) Internal data bus Match INTT2 P0MOD<PWM0INT> Interrupt control PFFCR<FF2TRG1:0> PFFCR<FF2C1:0> TO2 Timer flip-flop control 8-bit up counter (UC2) Clear P0MOD <PWM0S1:0> 2 n − 1 overflow control Overflow S Register buffer write Shift from register buffer Match with TREG2 2 n − 1 overflow TREG 2 (Compared value) Register buffer Q2 Q3 Q2 (Up counter = Q1) (Up counter = Q2) Q1 |
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