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TMP86FS28DFG データシート(PDF) 121 Page - Toshiba Semiconductor |
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TMP86FS28DFG データシート(HTML) 121 Page - Toshiba Semiconductor |
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121 / 272 page ![]() Page 109 TMP86FS28DFG Figure 8-15 PPG Output Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs (fc = 16 MHz) Setting port LD (TC11CR), 10000111B ; Sets the PPG mode, selects the source clock LDW (TC11DRA), 007DH ; Sets the cycle (1 ms ÷ 27/fc ms = 007DH) LDW (TC11DRB), 0019H ; Sets the low-level pulse width (200 µs ÷ 27/fc = 0019H) LD (TC11CR), 10010111B ; Starts the timer Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc = 16 MHz) Setting port LD (TC11CR), 10000111B ; Sets the PPG mode, selects the source clock LDW (TC11DRA), 007DH ; Sets the cycle (1 ms ÷ 27/fc µs = 007DH) LDW (TC11DRB), 0019H ; Sets the low-level pulse width (200 µs ÷ 27/fc = 0019H) LD (TC11CR), 10010111B ; Starts the timer :: LD (TC11CR), 10000111B ; Stops the timer LD (TC11CR), 10000100B ; Sets the timer mode LD (TC11CR), 00000111B ; Sets the PPG mode, TFF11 = 0 LD (TC11CR), 00010111B ; Starts the timer Q R D PPG pin Function output Port output enable I/O port output latch shared with PPG output Data output Toggle Set Clear Q TC11CR<TFF11> Write to TC11CR Internal reset Match to TC11DRB Match to TC11DRA TC11CR<TC11S> clear Timer F/F11 INTTC11 interrupt request |
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