TMP86FS28DFG datasheet(171/272 Pages) TOSHIBA

171 / 272 page

Page 159

TMP86FS28DFG

Figure 11-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)

11.6.3 8-bit transfer / receive mode

After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first

to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1<SIOS> to “1”.

When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving,

the data are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit

data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when

the number of data words specified with the SIOCR2<BUF> has been transferred. Usually, read the receive

data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and

receiving; therefore, always write the data to be transmitted after reading the all received data.

When the internal clock is used, a wait is initiated until the received data are read and the next transfer data

are written. A wait will not be initiated if even one transfer data word has been written.

When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is

necessary to read the received data and write the data to be transmitted next before starting the next shift oper-

ation. When an external clock is used, the transfer speed is determined by the maximum delay between genera-

tion of an interrupt request and the received data are read and the data to be transmitted next are written.

The transmit/receive operation is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to

“1” in INTSIO interrupt service program.

When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>

cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted.

That the transmitting/receiving has ended can be determined from the status of SIOSR<SIOF>.

SIOSR<SIOF> is cleared to “0” when the transmitting/receiving is ended.

When SIOCR1<SIOINH> is set, the transmit/receive operation is immediately ended and SIOSR<SIOF> is

cleared to “0”.

If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be

cleared to “0”, then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to

“0”.

If it is necessary to change the number of words in internal clock, during automatic-wait operation which

occurs after completion of transmit/receive operation, SIOCR2<BUF> must be rewritten before reading and

writing of the receive/transmit data.

DBR

Clear SIOS

Read out

SCK pin

(Output)

SI pin

INTSIO Interrupt

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

TMP86FS28DFG データシート(PDF) 171 Page - Toshiba Semiconductor

TMP86FS28DFG データシート(HTML) 171 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード