ST10F271 datasheet(137/173 Pages) STMICROELECTRONICS

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ST10F271

Electrical characteristics

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equal to the conversion rate of a single channel (maximum when fixed channel continuous

conversion mode is selected), it can be seen as a resistive path to ground. For instance,

assuming a conversion rate of 250kHz, with CS equal to 4pF, a resistance of 1MΩ is

obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered

channel). To minimize the error induced by the voltage partitioning between this resistance

(sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit

must be designed to respect the following relation:

The formula above provides a constraints for external network design, in particular on

resistive path.

A second aspect involving the capacitance network shall be considered. Assuming the three

capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the

equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch

close), a charge sharing phenomena is installed.

Figure 41.

Charge sharing timing diagram during sampling phase

In particular two different transient periods can be distinguished (see Figure 41):

●

A first and quick charge transfer from the internal capacitance CP1 and CP2 to the

sampling capacitance CS occurs (CS is supposed initially completely discharged):

considering a worst case (since the time constant in reality would be faster) in which

CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS

are in series, and the time constant is:

This relation can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D Converter circuitry has been

designed to be robust also in the very worst case: the sampling time TS is always much

longer than the internal time constant:

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the

voltage VA1 on the capacitance according to the following equation:

●

A second charge transfer involves also CF (that is typically bigger than the on-chip

capacitance) through the resistance RL: again considering the worst case in which CP2

------------------------------------------------------------------------------

⋅

---LSB

VA1

VA2

VCS

Voltage Transient on CS

∆V < 0.5 LSB

1 < (RSW + RAD) CS << TS

2 = RL (CS + CP1 + CP2)

()

⋅

-----------------------

⋅

()

⋅

()

⋅

()

⋅

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