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ST10F271 データシート(PDF) 158 Page - STMicroelectronics

部品番号 ST10F271
部品情報  16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
PDF  173 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F271 データシート(HTML) 158 Page - STMicroelectronics

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Electrical characteristics
ST10F271
158/173
1.
RW-delay and tA refer to the next following bus cycle.
2.
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3.
Partially tested, guaranteed by design characterization.
t38
CC
ALE falling edge to Latched
CS
– 4 – tA
6 – tA
– 4 – tA
6 – tA
ns
t39
SR
Latched CS low to Valid Data
In
16.5 +
+ tC + 2tA
3TCL – 21 +
+ tC + 2tA
ns
t41
CC
Latched CS hold after RD,
WR
2 + tF
TCL – 10.5 + tF
–ns
t82
CC
Address setup to RdCS,
WrCS
(with RW-delay)
14 + 2tA
2TCL – 11 + 2tA
–ns
t83
CC
Address setup to RdCS,
WrCS
(no RW-delay)
2 + 2tA
TCL –10.5 + 2tA
–ns
t46
SR
RdCS to Valid Data In
(with RW-delay)
–4 + tC
2TCL – 21 + tC
ns
t47
SR
RdCS to Valid Data In
(no RW-delay)
–16.5 + tC
3TCL – 21 + tC
ns
t48
CC
RdCS, WrCS Low Time
(with RW-delay)
15.5 + tC
2TCL – 9.5 + tC
–ns
t49
CC
RdCS, WrCS Low Time
(no RW-delay)
28 + tC
3TCL – 9.5 + tC
–ns
t50
CC
Data valid to WrCS
10 + tC
2TCL – 15 + tC
–ns
t51
SR
Data hold after RdCS
0–
0
ns
t53
SR
Data float after RdCS
(with RW-delay) 3
16.5 + tF
2TCL – 8.5 + tF
ns
t68
SR
Data float after RdCS
(no RW-delay) 3
–4 + tF
TCL – 8.5 + tF
ns
t55
CC
Address hold after
RdCS, WrCS
– 8.5 + tF
– 8.5 + tF
–ns
t57
CC
Data hold after WrCS
2 + tF
TCL – 10.5 + tF
–ns
Table 78.
Demultiplexed bus timings (continued)
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
min.
max.



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