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ST10F271 データシート(PDF) 163 Page - STMicroelectronics

部品番号 ST10F271
部品情報  16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
PDF  173 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F271 データシート(HTML) 163 Page - STMicroelectronics

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ST10F271
Electrical characteristics
163/173
1.
These timings are given for characterization purposes only, in order to assure recognition at a specific
clock edge.
2.
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers
to the current bus cycle.
Table 79.
CLKOUT and READY timings
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
min.
max.
t29
CC
CLKOUT cycle time
25
25
2TCL
2TCL
ns
t30
CC
CLKOUT high time
9
–
TCL – 3.5
–
ns
t31
CC
CLKOUT low time
10
–
TCL – 2.5
–
ns
t32
CC
CLKOUT rise time
–
4
–
4
ns
t33
CC
CLKOUT fall time
–
4
–
4
ns
t34
CC
CLKOUT rising edge to
ALE falling edge
– 2 + tA
8 + tA
– 2 + tA
8 + tA
ns
t35
SR
Synchronous READY
setup time to CLKOUT
17
–
17
–
ns
t36
SR
Synchronous READY
hold time after CLKOUT
2–
2
–
ns
t37
SR
Asynchronous READY
low time
35
–
2TCL + 10
–
ns
t58
SR
Asynchronous READY
setup time 1
17
–
17
–
ns
t59
SR
Asynchronous READY
hold time 1
2–
2
–
ns
t60
SR
Async. READY hold time after
RD, WR high (Demultiplexed
Bus) 2
02tA + tC + tF
02tA + tC + tF
ns



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