データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

WM8994ECS/R データシート(PDF) 284 Page - Cirrus Logic

部品番号 WM8994ECS/R
部品情報  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R データシート(HTML) 284 Page - Cirrus Logic

Back Button WM8994ECS/R Datasheet HTML 280Page - Cirrus Logic WM8994ECS/R Datasheet HTML 281Page - Cirrus Logic WM8994ECS/R Datasheet HTML 282Page - Cirrus Logic WM8994ECS/R Datasheet HTML 283Page - Cirrus Logic WM8994ECS/R Datasheet HTML 284Page - Cirrus Logic WM8994ECS/R Datasheet HTML 285Page - Cirrus Logic WM8994ECS/R Datasheet HTML 286Page - Cirrus Logic WM8994ECS/R Datasheet HTML 287Page - Cirrus Logic WM8994ECS/R Datasheet HTML 288Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 284 / 363 page
background image
WM8994
284
Rev 4.6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R517 (0205h)
AIF2
Clocking (2)
5:3
AIF2DAC_DIV
[2:0]
000
Selects the AIF2 input path sample rate relative to the AIF2
output path sample rate.
This field should only be changed from default in modes
where the AIF2 input path sample rate is slower than the
AIF2 output path sample rate.
000 = Divide by 1
001 = Divide by 1.5
010 = Divide by 2
011 = Divide by 3
100 = Divide by 4
101 = Divide by 5.5
110 = Divide by 6
111 = Reserved
2:0
AIF2ADC_DIV
[2:0]
000
Selects the AIF2 output path sample rate relative to the
AIF2 input path sample rate.
This field should only be changed from default in modes
where the AIF2 output path sample rate is slower than the
AIF2 input path sample rate.
000 = Divide by 1
001 = Divide by 1.5
010 = Divide by 2
011 = Divide by 3
100 = Divide by 4
101 = Divide by 5.5
110 = Divide by 6
111 = Reserved
Register 0205h AIF2 Clocking (2)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R520 (0208h)
Clocking (1)
4
TOCLK_ENA
0
Slow Clock (TOCLK) Enable
0 = Disabled
1 = Enabled
This clock is required for zero-cross timeout.
3
AIF1DSPCLK_E
NA
0
AIF1 Processing Clock Enable
0 = Disabled
1 = Enabled
2
AIF2DSPCLK_E
NA
0
AIF2 Processing Clock Enable
0 = Disabled
1 = Enabled
1
SYSDSPCLK_E
NA
0
Digital Mixing Processor Clock Enable
0 = Disabled
1 = Enabled
0
SYSCLK_SRC
0
SYSCLK Source Select
0 = AIF1CLK
1 = AIF2CLK
Register 0208h Clocking (1)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com