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IS25LE128E-RMLA3:P-TY データシート(PDF) 143 Page - Integrated Silicon Solution, Inc

部品番号 IS25LE128E-RMLA3:P-TY
部品情報  SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  197 Pages
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メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE128E-RMLA3:P-TY データシート(HTML) 143 Page - Integrated Silicon Solution, Inc

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IS25LE256E/128E
IS25WE256E/128E
Integrated Silicon Solution, Inc.- www.issi.com
143
Rev.A9
03/07/2023
Figure 8.95 FRQDTR Sequence In QPI Mode (EDh [EXTADD=1] or EEh, 4-byte address)
Instruction
= EDh/EEh
CE #
SCK
4-byte Address
0
1
2
3
4
5
6
7
8
9
10
11
12
Mode 3
Mode 0
tV
28 24 20
5 1
29 25 21
4 0
IO0
IO1
30 26 22
31 27 23
16 12 8
17 13 9
18 14 10
19 15 11
6 Dummy Cycles
IO2
IO3
6 2
7 3
Data
Out
5 1
4 0
6 2
7 3
Mode Bits
...
4
0
5
1
6
2
7
3
...
...
...
...
4
0
5
1
6
2
7
3
Notes:
1.
If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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