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IS25LE128E-RMLA3:P-TY データシート(PDF) 179 Page - Integrated Silicon Solution, Inc

部品番号 IS25LE128E-RMLA3:P-TY
部品情報  SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  197 Pages
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メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE128E-RMLA3:P-TY データシート(HTML) 179 Page - Integrated Silicon Solution, Inc

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IS25LE256E/128E
IS25WE256E/128E
Integrated Silicon Solution, Inc.- www.issi.com
179
Rev.A9
03/07/2023
8.70 WRITE ECC REGISTER OPERATION (WRECC, B5h)
Before the Write ECC Register (WRECC) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable the WRECC operation.
The WRECC command (B5h) is entered by shifting the instruction and data byte on SI.
CE# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WRECC
command is not executed. As soon as CE# is driven to the logic high state, the WRECC operation is initiated with
no delays.
Figure 8.154 WRECC Sequence In SPI Mode
Instruction = B5h
CE #
SCK
SI
SO
Data In
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
7
3
2
1
0
6
5
4
High Impedence
Figure 8.155 WRECC Sequence In QPI Mode
B5h
0
1
Mode 3
Mode 0
2
3
7:4
3:0
CE#
SCK
IO[3:0]
Data In



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