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IS25LEG-RLLA2:P-TY データシート(PDF) 173 Page - Integrated Silicon Solution, Inc

部品番号 IS25LEG-RLLA2:P-TY
部品情報  SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  193 Pages
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メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LEG-RLLA2:P-TY データシート(HTML) 173 Page - Integrated Silicon Solution, Inc

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IS25LE01GG
IS25WE01GG
Integrated Silicon Solution, Inc.- www.issi.com
173
Rev. A3
10/02/2025
8.69 READ DLP OPERATION (RDDLP, 41h)
The instruction is shifted on SI, then the 8-bit DLP from VDLR is shifted out on SO. It is possible to read the DLP
continuously by providing multiples of eight clock cycles.
Figure 8.153 RDDLP Sequence In SPI Mode
Instruction = 41h
CE#
SCK
SI
SO
0
1
...
7
8
9
...
15
16
17
...
23
...
64
65
...
Mode 3
Mode 0
tV
7
7
6
0
6
...
0
7
6
0
...
...
...
71
Register Read
Repeat Register Read
...
Repeat Register Read
Figure 8.154 RDDLP Sequence In QPI Mode
41h
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0
2
3
4
5
tV
...
16
17
7 : 0
7 : 0
...
7 : 0
Register
Read
Repeat
Register
Read
Repeat
Register
Read



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