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ADE7166ACPZF16 データシート(PDF) 111 Page - Analog Devices |
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ADE7166ACPZF16 データシート(HTML) 111 Page - Analog Devices |
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111 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 111 of 144 Mode 0 (13-Bit Timer/Counter) Table 106. Timer 0 High Byte SFR (TH0, 0x8C) Bit Mnemonic Default Description Mode 0 configures an 8-bit timer/counter. Figure 95 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single cycle core. 7 to 0 TH0 0 Timer 0 Data High Byte. Table 107. Timer 0 Low Byte SFR (TL0, 0x8A) CONTROL TR0 TF0 TL0 (5 BITS) TH0 (8 BITS) INTERRUPT P0.6/T0 GATE INT0 fCORE C/T0 = 0 C/T0 = 1 Bit Mnemonic Default Description 7 to 0 TL0 0 Timer 0 Data Low Byte. Table 108. Timer 1 High Byte SFR (TH1, 0x8D) Bit Mnemonic Default Description 7 to 0 TH1 0 Timer 1 Data High Byte. Table 109. Timer 1 Low Byte SFR (TL1, 0x8B) Bit Mnemonic Default Description 7 to 0 TL1 0 Timer 1 Data Low Byte. Figure 95. Timer/Counter 0, Mode 0 In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag, TF0. TF0 can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate0 = 0 or Table 110. Timer 2 High Byte SFR (TH2, 0xCD) Bit Mnemonic Default Description 7 to 0 TH2 0 Timer 2 Data High Byte. Table 111. Timer 2 Low Byte SFR (TL2, 0xCC) INT0 = 1. Setting Gate0 = 1 allows the timer to be controlled by external input Bit Mnemonic Default Description INT0 to facilitate pulse width measurements. TR0 is a control bit in the Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88); the Gate bit is in Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89). The 13-bit register consists of all 8 bits of Timer 0 High Byte SFR (TH0, 0x8C) and the lower 5 bits of Timer 0 Low Byte SFR (TL0, 0x8A). The upper three bits of TL0 SFR are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. 7 to 0 TL2 0 Timer 2 Data Low Byte. Table 112. Timer 2 Reload/Capture High Byte SFR (RACP2H, 0xCB) Bit Mnemonic Default Description 7 to 0 TH2 0 Timer 2 Reload/ Capture High Byte. Table 113. Timer 2 Reload/Capture Low Byte SFR (RACP2L, 0xCA) Mode 1 (16-Bit Timer/Counter) Bit Mnemonic Default Description Mode 1 is the same as Mode 0 except that the Mode 1 timer register runs with all 16 bits. Mode 1 is shown in 7 to 0 TL2 0 Timer 2 Reload/ Capture Low Byte. Figure 96. CONTROL TR0 TF0 TL0 (8 BITS) TH0 (8 BITS) INTERRUPT 0 P0.6/T0 GATE INT C/T0 = 0 C/T0 = 1 fCORE TIMER 0 AND TIMER 1 Timer/Counter 0 and Timer/Counter 1 Data Registers Each timer consists of two 8-bit registers. They are Timer 0 High Byte SFR (TH0, 0x8C), Timer 0 Low Byte SFR (TL0, 0x8A), Timer 1 High Byte SFR (TH1, 0x8D), and Timer 1 Low Byte SFR (TL1, 0x8B) These can be used as independent registers or combined into a single 16-bit register, depending on the timer mode configuration (see Table 106 to Table 109). Timer/Counter 0 and Timer/Counter 1 Operating Modes Figure 96. Timer/Counter 0, Mode 1 This section describes the operating modes for Timer/Counter 0 and Timer/Counter 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1. |
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