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IS25LP02GJ-RHLA3 データシート(PDF) 136 Page - Integrated Silicon Solution, Inc

部品番号 IS25LP02GJ-RHLA3
部品情報  SERIAL FLASH MEMORY 166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  182 Pages
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メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP02GJ-RHLA3 データシート(HTML) 136 Page - Integrated Silicon Solution, Inc

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IS25LP02GJ
IS25WP02GJ
Integrated Silicon Solution, Inc.- www.issi.com
136
Rev.A
10/02/2025
Figure 8.94 FRQDTR AX Read Sequence (EDh [EXTADD=1] or EEh, 4-byte address)
CE #
SCK
4-byte Address
0
1
2
3
4
5
6
7
8
9
10
11
Mode 3
Mode 0
tV
28 24 20
5 1
29 25 21
4 0
IO0
IO1
30 26 22
31 27 23
16 12
0
17 13
1
18 14
2
19 15
3
6 Dummy Cycles
IO2
IO3
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
Data
Out
Data
Out
Data
Out
Data
Out
5 1
4 0
6 2
7 3
Mode Bits
12
13
...
8 4
9 5
10 6
11 7
...
...
...
...
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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