AS3722 datasheet(177/199 Pages) AMSOSRAM

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[v1-01] 2015-Sep-07

AS3722 − Register Description

Figure 215:

Fuse12

Figure 216:

Fuse13

Addr:ach

Fuse12

Bit

Bit Name

Default

Access

Bit Description

7:6

sdmph_clk_div

Divide clock of SD0,SD1,SD6 by 1,2 or 4

0 : 2.7MHz

1 : 1.35MHz

2 : 0.675MHz

3 : 0.675MHz

5:4

wtdg_mode

defines actions when the watchdog expires

0 : interrupt only

1 : performs a reset cycle, then try restart

2 : power-off

3 : performs up to 2 reset cycles, then

power-off

3wtdg_on

Enable the watch dog timer. Expiry of the timer

will reset the device (see WatchdogControl).

2enable3_inv

Sets the polarity of the ENABLE3 pin

0 : High active for ENABLE3

1 : Inverted: Low active for ENABLE3

1enable2_inv

Sets the polarity of the ENABLE2 pin

0 : High active for ENABLE2

1 : Inverted: Low active for ENABLE2

0therm_inv

Sets the polarity of the THERM pin

0 : High active for THERM event

1 : Inverted: Low active for THERM event

Addr:adh

Fuse13

Bit

Bit Name

Default

Access

Bit Description

7:6

sd0_vmax_0

5:4

sd6_trim_gm

3:2

sd1_trim_gm

1:0

sd0_trim_gm

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