ST10F280 datasheet(172/186 Pages) STMICROELECTRONICS

172 / 186 page

ST10F280

172/186

Notes: 1. RW-delay and

A refer to the next following bus cycle.

2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address

changes before the end of RD have no impact on read cycles.

3. Partially tested, guaranteed by design characterization.

t41 CC

Latched CS hold after RD, WR

2 + tF

–

TCL - 10.5 + tF

–ns

t82 CC

Address setup to RdCS, WrCS

(with RW-delay)

14.5 + 2tA

–

2 TCL - 10.5 +

2tA

–ns

t83 CC Address setup to RdCS, WrCS

(no RW-delay)

2 + 2tA

–

TCL - 10.5 + 2tA

–ns

t46 SR

RdCS to Valid Data In

(with RW-delay)

–4 + tC

–

2 TCL - 21 + tC

t47 SR

RdCS to Valid Data In

(no RW-delay)

–

16.5 + tC

–

3 TCL - 21 + tC

t48 CC

RdCS, WrCS Low Time

(with RW-delay)

15.5 + tC

–

2 TCL - 9.5

+ tC

–ns

t49 CC RdCS, WrCS Low Time

(no RW-delay)

28 + tC

–

3 TCL - 9.5 + tC

–ns

t50 CC Data valid to WrCS

10 + tC

–

2 TCL - 15 + tC

–ns

t51 SR

Data hold after RdCS

0–

–

t53 SR

Data float after RdCS

(with RW-delay)

–

16.5 + tF

–

2 TCL - 8.5 + tF

t68 SR

Data float after RdCS

(no RW-delay)

–4 + tF

–

TCL - 8.5 + tF

t55 CC

Address hold after

RdCS, WrCS

-8.5 + tF

–

-8.5 + tF

–ns

t57 CC

Data hold after WrCS

2 + tF

–

TCL - 10.5 + tF

–ns

Table 42 : Demultiplexed Bus Characteristics

Symbol

Parameter

Maximum CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

Minimum

Maximum

Minimum

Maximum

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