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データシートサーチシステム |
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データシートサーチシステム |
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4250 データシート(PDF) 17 Page - Renesas Technology Corp |
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4250 データシート(HTML) 17 Page - Renesas Technology Corp |
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17 / 59 page  16 MITSUBISHI MICROCOMPUTERS 4250 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER • Program counter (PC) ........... Each interrupt address • Stack register (SK) • Interrupt enable flag (INTE) ...... 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) ...................................................................... 0 • Data pointer, carry flag, skip flag ......... Stored in the interrupt stack register (SDP) automatically The address of main routine to be executed when returning Fig. 14 Internal state when interrupt occurs T1F V11 EXF0 V10 Address 2 in page 1 Address 0 in page 1 Request flag (state retained) Enable bit Enable flag Activated condition INT pin (L →H or H →L input) Timer 1 underflow EI RTI Interrupt service routine Interrupt occurs Interrupt is enabled Main routine : Interrupt enabled state : Interrupt disabled state (4) Internal state during an interrupt The internal state of the microcomputer during an in- terrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disa- bled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.” • Data pointer, carry flag and skip flag The contents of these pointer and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store se- quence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return to main routine. Interrupt enabled by executing the EI instruction is per- formed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI in- struction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing Fig. 15 Interrupt system diagram |
同様の部品番号 - 4250 |
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同様の説明 - 4250 |
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