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M32C/8B データシート(PDF) 149 Page - Renesas Technology Corp |
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M32C/8B データシート(HTML) 149 Page - Renesas Technology Corp |
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149 / 406 page ![]() Under development M32C/8B Group 13. DMAC Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 132 of 385 Figure 13.9 DMA Transfers Triggered by INT Interrupt Requests BCLK DMA0 DMA1 CPU INT0 INT1 DRQ bit in DMA0 DRQ bit in DMA1 Example when DMA transfer requests for DMA0 and DMA1 are generated simultaneously and DMA transfers (SFR to RAM) are performed in minimum time. Bus privilege acquired |
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