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M32C/8B データシート(PDF) 160 Page - Renesas Technology Corp |
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M32C/8B データシート(HTML) 160 Page - Renesas Technology Corp |
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160 / 406 page ![]() Under development M32C/8B Group 15. Timer A Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 143 of 385 15.1 Timer A Timer A contains the following four modes. Except in event counter mode, all timers A0 to A4 have the same functionality. Bits TMOD1 and TMOD0 in the TAiMR register (i = 0 to 4) determine which mode is used. • Timer mode: The timer counts the internal count source. • Event counter mode: The timer counts overflow/underflow signal of another timer or the external pulses. • One-shot timer mode: The timer operates only once for one trigger. • Pulse width modulation mode: The timer continuously outputs given pulse widths. Figure 15.3 shows a block diagram of timer A. Figures 15.4 to 15.13 show the registers associated with timer A. Table 15.1 lists TAiOUT pin settings to use in output mode. Table 15.2 lists TAiIN and TAiOUT pin settings to use in input mode. Figure 15.3 Timer A Block Diagram Reload register 00 01 10 11 Clock source select Clock select TAiS Polarity Selector High-order bits of data bus 8 low-order bits 8 high-order bits Increment/decrement TAiUD Toggle flip flop MR2 TMOD1 and TMOD0 Decrement Function select register TAiOUT TAiIN TAiTGH to TAiTGL · Event counter mode · Timer Mode (Gate Function) · Timer mode · One-shot timer mode · Pulse width modulation mode TMOD1 and TMOD0, MR2 TCK1 and TCK0 TB2 Overflow(2) TAj Overflow(2) TAk Overflow(2) i = 0 to 4 j = i - 1, except j = 4 if i = 0 k = i + 1, except k = 0 if i = 4 NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Overflow signal or underflow signal. TCK1 and TCK0, TMOD1 and TMOC0, MR2 and MR1: Bits in the TAiMR register TAiTGH to TAiTGL: Bits in the ONSF register if i = 0 or bits in the TRGSR register if i = 1 to 4 TAiS: Bit in the TABSR register TAiUD: Bit in the UDF register f1 f8 f2n(1) fC32 00 01 10 11 0 1 Counter 11 00 01 10 11 Low-order bits of data bus TAi Addresses TAj TAk Timer A0 0347h 0346h Timer A4 Timer A1 Timer A1 0349h 0348h Timer A0 Timer A2 Timer A2 034Bh 034Ah Timer A1 Timer A3 Timer A3 034Dh 034Ch Timer A2 Timer A4 Timer A4 034Fh 034Eh Timer A3 Timer A0 Always decrement except in event counter mode |
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