M32CSLASH8B datasheet(191/406 Pages) RENESAS

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Under development

M32C/8B Group

15. Timer B

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 174 of 385

15.2.2

Event Counter Mode

In event counter mode, the timer counts overflows/underflows of another timer, or the external pulses.

Table 15.10 lists specifications of event counter mode. Figure 15.28 shows an event counter mode operation.

Table 15.10

Specifications of Event Counter Mode

NOTE:

1. Wait for one or more count source cycles to write after the count starts.

Figure 15.28

Operation in Event Counter Mode (Timer B)

Item

Specification

Count source

• External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected

by a program)

• TBj overflows or underflows (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3)

Count operation

• Counter decrements

When the timer underflows, the contents of the reload register are reloaded into

the counter and the count continues.

Number of counting

(n + 1) times

n: Setting value of the TBi register 0000h to FFFFh

Count start condition

The TBiS bit in the TABSR or TBSR register is set to 1 (count starts)

Count stop condition

The TBiS bit is set to 0 (count stops)

Interrupt request generation timing When the timer underflows

TBiIN pin function

Count source input

Read from timer

A read from the TBi register returns a counter value.

Write to timer

• A write to the TBi register while the count is stopped:

The value is written to both the reload register and the counter.

• A write to the TBi register while counting:

The value is written to the reload register (It is transferred to the counter at the

next reload timing).(1)

Count starts

FFFFh

TBiS bit in the TABSR or TBSR

regsiter

Contents of the counter

n = contents of the reload

0000h

IR bit in the TBiIC regsiter

(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode)

Bits MR1 and MR0 are set to 00b (count the falling edge of the external signal)

The TCK1 bit is set to 0 (signal input to TBiIN pin)

Underflow

Reload

Count stops

Set to 0 by an interrupt request acknowledgement or by a program

Count resumes

Input to the TBiIN pin

i = 0 to 5

“H”

“L”

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