X25020

1

2K

X25020

256 x 8 Bit

©Xicor, Inc. 1994, 1995, 1996 Patents Pending

Characteristics subject to change without notice

3834-1.8 6/10/96 T3/C1/D0 NS

3834 FHD F01

FUNCTIONAL DIAGRAM

A V AILABLE

AN9 • AN18 • AN31 • AN37 • AN40

DESCRIPTION

nally organized as 256 x 8. The X25020 features a serial

interface and software protocol allowing operation on a

simple three-wire bus. The bus signals are a clock input

(SCK) plus separate data in (SI) and data out (SO) lines.

Access to the device is controlled through a chip select

(

CS) input, allowing any number of devices to share the

same bus.

The X25020 also features two additional inputs that

provide the end user with added flexibility. By asserting

the

HOLD input, the X25020 will ignore transitions on its

inputs, thus allowing the host to service higher priority

interrupts. The

WP input can be used as a hardwire input

to the X25020 disabling all write attempts, thus providing

a mechanism for limiting end user capability of altering

the memory.

The X25020 utilizes Xicor’s proprietary Direct Write™

cell, providing a minimum endurance of 100,000 cycles

per byte and a minimum data retention of 100 years.

FEATURES

—4 Byte Page Mode

—10

—3mA Active Write Current

—Power-Up/Power-Down protection circuitry

—Write Latch

—Write Protect Pin

—5ms Write Cycle Time (Typical)

—Endurance: 100,000 cycles per byte

—Data Retention: 100 Years

—ESD protection: 2000V on all pins

COMMAND

DECODE

AND

CONTROL

LOGIC

WRITE

CONTROL

AND

TIMING

LOGIC

WRITE

PROTECT

LOGIC

X DECODE

LOGIC

256 BYTE

ARRAY

16 X 32

Y DECODE

DATA REGISTER

16 X 32

32 X 32

SO

SI

SCK

CS

HOLD

WP

16

16

32

8

4

STATUS

REGISTER