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PIC12F1822-I/MF データシート(PDF) 123 Page - Microchip Technology |
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PIC12F1822-I/MF データシート(HTML) 123 Page - Microchip Technology |
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123 / 398 page  2010 Microchip Technology Inc. Preliminary DS41413A-page 123 PIC12F/LF1822/16F/LF1823 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA TABLE 12-2: SUMMARY OF CONFIGURATION WORD WITH PORTA REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUB<5:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — —ANSA4 — ANSA2 ANSA1 ANSA0 122 APFCON RXDTSEL SDOSEL SSSEL --- T1GSEL TXCKSEL P1BSEL CCP1SEL 118 LATA — —LATA5 LATA4 —LATA2 LATA1 LATA0 122 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 171 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 121 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 121 WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 123 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC12F1822/16F1823 only. 2: PIC16F/LF1823 only. Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register on Page CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD 50 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC12F1822/16F1823 only. |
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